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data sheet 1997 description the m pd78081(a) and 78082(a) are members of the m pd78083 subseries of the 78k/0 series microcontrollers. these products are produced with a more stringent quality assurance program than that of the m pd78081 and 78082 (standard models) (nec classifies these products as special products by quality grade). besides a high-speed, high-performance cpu, these microcontrollers have on-chip rom, ram, i/o ports, 8-bit resolution a/d converter, timer, serial interface, interrupt control, and other peripheral hardware. the m pd78p083(a) including a one-time prom version which can operate in the same power supply voltage range as a mask rom version, and various development tools are available. the details of the functions are described in the following users manuals. be sure to read the documents before starting design. m pd78083 subseries users manual : ieu-1407 78k/0 series users manual instructions : ieu-1372 features ? internal rom and ram program memory data memory (rom) (internal high-speed ram) m pd78081(a) 8 kbytes 256 bytes 44-pin plastic qfp (10 10 mm) m pd78082(a) 16 kbytes 384 bytes ? minimum instruction execution time can be changed from high-speed (0.4 m s) to low-speed (12.8 m s) ? i/o ports: 33 ? 8-bit resolution a/d converter : 8 channels ? serial interface : 1 channel 3-wire serial i/o/uart mode : 1 channel ? timer : 3 channels ? supply voltage : v dd = 1.8 to 5.5 v application fields controllers for automobile electronic control systems, gas detector circuit-breakers, various types of safety equipment, etc. in addition to the m pd78081(a) and 78082(a), this data sheet also describes the m pd78081(a2). unless otherwise specified, however, the m pd78081(a) and 78082(a) are used throughout this data sheet as the representative products, and their descriptions also apply to the m pd78081(a2). document no. u12436ej1v0ds00 (1st edition) date published july 1997 n printed in japan the information in this document is subject to change without notice. part number item package 8-bit single-chip microcontroller mos integrated circuit m pd78081(a), 78082(a)
2 m pd78081(a), 78082(a) ordering information part number package m pd78081gb(a)- -3b4 44-pin plastic qfp (10 10 mm) m pd78081gb(a)- -3bs-mtx note 44-pin plastic qfp (10 10 mm) m pd78082gb(a)- -3b4 44-pin plastic qfp (10 10 mm) m pd78082gb(a)- -3bs-mtx note 44-pin plastic qfp (10 10 mm) m pd78081gb(a2)- -3b4 44-pin plastic qfp (10 10 mm) note under planning caution m pd78081gb(a) and 78082gb(a) have two kinds of package (refer to 11. package drawings). please consult nec?s sales representative for the available package. remark indicates rom code suffix. quality grade special please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. differences between m pd78081 and 78082, and m pd78081(a) and 78082(a) part number m pd78081, 78082 m pd78081(a), 78082(a) item quality grade standard special package 42-pin plastic shrink dip (600 mil) 44-pin plastic qfp (10 10 mm) 44-pin plastic qfp (10 10 mm) differences between m pd78081(a) and 78081(a2) part number m pd78081(a) m pd78081(a2) item supply voltage v dd = 1.8 to 5.5 v v dd = 5 v 10% minimum instruction execution 0.4 m s (at 5 mhz) 0.57 m s (at 7 mhz) time operating ambient temperature t a = e40 to 85?c t a = e40 to +125?c remark in addition to the above parameters, the supply current also differs. for details, refer to 10. electrical specifications .
3 m pd78081(a), 78082(a) 78k/0 series development the following shows the 78k/0 series products development. subseries names are shown inside frames. note under planning pd78014 pd78002 pd78083 pd78002y 100-pin 100-pin 100-pin 64-pin 64-pin 64-pin 42/44-pin control y subseries products are compatible with i 2 c bus. a timer was added to the pd78054, and the external interface function was enhanced. emi noise reduction version of the pd78078. rom-less versions of the pd78078. an a/d converter and 16-bit timer were added to the pd78002. an a/d converter was added to the pd78002. basic subseries for control. on-chip uart, capable of operating at a low voltage (1.8 v). pd780018ay 100-pin serial i/o of the pd78078y was enhanced, and only selected functions are provided. pd78078 pd78070a pd78075b pd78070ay m m mm m mm m mm m m m m m m inverter control pd780964 64-pin m an a/d converter of the pd780924 was enhanced. pd78078y m m pd78075by pd78018f pd780001 pd78018fy pd78014y 80-pin 80-pin 64-pin 78k/0 series products in mass production products under development emi noise reduction version of the pd78054. uart and d/a converter were added to the pd78014, and i/o was enhanced. low-voltage (1.8 v) operation versions of the pd78014 with several rom and ram capacities available. an a/d converter of the pd780024 was enhanced. emi noise reduction version of the pd78018f. on-chip inverter control circuit and uart, emi noise reduction version. serial i/o of the pd78018f was enhanced, emi noise reduction version. serial i/o of the pd78054 was enhanced, emi noise reduction version. pd780058 80-pin m mm pd780034 pd780024 pd78014h pd780034y pd780024y 64-pin 64-pin 64-pin mm mm m m m m m m m m m fip tm drive pd78044f 100-pin 80-pin 80-pin m m the i/o and fip c/d of the pd78044f were enhanced, display output total: 53 the i/o and fip c/d of the pd78044h were enhanced, display output total: 48 n-ch open-drain input/output was added to the pd78044f, display output total: 34 basic subseries for driving fip, display output total: 34 m m 100-pin pd780924 64-pin m pd780308 pd78064b pd78064 100-pin 100-pin 100-pin m m sio of the pd78064 was enhanced, and rom and ram were expanded. emi noise reduction version of the pd78064. basic subseries for driving lcds, on-chip uart. m pd780308y m pd78064y m lcd drive m m lv pd78p0914 64-pin m on-chip pwm output, lv digital code decoder, hsync counter. pd78054 m pd78054y m pd78058fy m pd780058y note m pd78058f m pd78044h m m pd780228 pd780208 m m m iebus tm supported pd78098b 80-pin m emi noise reduction version of the pd78098. the iebus controller was added to the pd78054. pd78098 80-pin m m meter control pd780973 80-pin m on-chip automobile meter driving controller/driver.
4 m pd78081(a), 78082(a) the following table shows the differences among subseries functions. function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control m pd78075b 32 k to 40 k 4ch 1ch 1ch 1ch 8ch e 2ch 3ch (uart: 1ch) 88 1.8 v available m pd78078 48 k to 60 k m pd78070a e 61 2.7 v m pd780058 24 k to 60 k 2ch 2ch 3ch (time-division uart: 1ch) 68 1.8 v m pd78058f 48 k to 60 k 3ch (uart: 1ch) 69 2.7 v m pd78054 16 k to 60 k 2.0 v m pd780034 8 k to 32 k e 8ch e 3ch (uart: 1ch, 51 1.8 v m pd780024 8ch e time-division 3-wire: 1ch) m pd78014h 2ch 53 m pd78018f 8 k to 60 k m pd78014 8 k to 32 k 2.7 v m pd780001 8 k e e 1ch 39 e m pd78002 8 k to 16 k 1ch e 53 available m pd78083 e 8ch 1ch (uart: 1ch) 33 1.8 v e inverter m pd780964 8 k to 32 k 3ch note e 1ch e 8ch e 2ch (uart: 2ch) 47 2.7 v available control m pd780924 8ch e fip m pd780208 32 k to 60 k 2ch 1ch 1ch 1ch 8ch e e 2ch 74 2.7 v e drive m pd780228 48 k to 60 k 3ch e e 1ch 72 4.5 v m pd78044h 32 k to 48 k 2ch 1ch 1ch 68 2.7 v m pd78044f 16 k to 40 k 2ch lcd m pd780308 48 k to 60 k 2ch 1ch 1ch 1ch 8ch e e 3ch (time-division uart: 1ch) 57 2.0 v e drive m pd78064b 32 k 2ch (uart: 1ch) m pd78064 16 k to 32 k iebus m pd78098b 40 k to 60 k 2ch 1ch 1ch 1ch 8ch e 2ch 3ch (uart: 1ch) 69 2.7 v available supported m pd78098 32 k to 60 k meter m pd780973 24 k to 32 k 3ch 1ch 1ch 1ch 5ch e e 2ch (uart: 1ch) 56 4.5 v e control lv m pd78p0914 32 k 6ch e e 1ch 8ch e e 2ch 54 4.5 v available note 10-bit timer: 1 channel min.
5 m pd78081(a), 78082(a) rom internal high-speed ram memory space general registers minimum instruction execution time instruction set i/o ports a/d converter serial interface timer timer output clock output buzzer output vectored interrupt sources supply voltage operating ambient temperature package overview of function m pd78081(a) m pd78082(a) 8 kbytes 256 bytes internal memory 16 kbytes 384 bytes 64 kbytes 8 bits 32 registers (8 bits 8 registers 4 banks) on-chip minimum instruction execution time selective function 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (at main system clock of 5.0 mhz) 16-bit operation multiply/divide (8 bits 8 bits,16 bits ? 8 bits) bit manipulation (set, reset, test, boolean operation) bcd adjustment, etc. total : 33 cmos input : 0 1 cmos i/o : 32 8-bit resolution 8 channels 3-wire serial i/o/uart mode selectable : 1 channel 8-bit timer/event counter : 2 channels watchdog timer : 1 channel 2 (8-bit pwm output) 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (at main system clock of 5.0 mhz) 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (at main system clock of 5.0 mhz) internal : 8, external : 3 internal : 1 1 v dd = 1.8 to 5.5 v t a = e40 to +85 c 44-pin plastic qfp (10 10 mm) item part number maskable non-maskable software caution the supply voltage and other parameters of the m pd78081(a2) differ from those of the other models. for details, refer to differences between m pd78081(a) and 78081(a2).
6 m pd78081(a), 78082(a) contents 1. pin configuration (top view) ................................................................................................... 7 2. block diagram ............................................................................................................................. 9 3. pin functions .............................................................................................................................. 1 0 3.1 port pins ............................................................................................................................... .................... 10 3.2 non-port pins ............................................................................................................................... ........... 11 3.3 pin i/o circuits and recommended connection of unused pins ................................................... 12 4. memory space ............................................................................................................................. 14 5. peripheral hardware functions ...................................................................................... 15 5.1 ports ............................................................................................................................... ........................... 15 5.2 clock generator ............................................................................................................................... ....... 16 5.3 timer/event counter ............................................................................................................................... 16 5.4 clock output control circuit ................................................................................................................. 18 5.5 buzzer output control circuit .............................................................................................................. 18 5.6 a/d converter ............................................................................................................................... ........... 19 5.7 serial interface ............................................................................................................................... ......... 20 6. interrupt functions ............................................................................................................... 21 7. standby function ..................................................................................................................... 24 8. reset function ........................................................................................................................... 24 9. instruction set .......................................................................................................................... 25 10. electrical specifications .................................................................................................... 28 11. package drawings ................................................................................................................... 49 12. recommended soldering conditions .............................................................................. 51 appendix a. development tools .............................................................................................. 52 appendix b. related documents .............................................................................................. 54
7 m pd78081(a), 78082(a) 1. pin configuration (top view) 44-pin plastic qfp (10 10 mm) m pd78081gb(a)- -3b4 m pd78081gb(a)- -3bs-mtx note m pd78082gb(a)- -3b4 m pd78082gb(a)- -3bs-mtx note m pd78081gb(a2)- -3b4 note under planning cautions 1. connect ic (internally connected) pin directly to v ss . 2. connect av dd pin to v dd . 3. connect av ss pin to v ss . 4. connect nc (non-connection) pin to v ss for noise protection (it can be left open). p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 p72/asck/sck2 p71/t x d/so2 p70/r x d/si2 p101/ti6/to6 p100/ti5/to5 p03/intp3 p02/intp2 p01/intp1 p00 p37 p36/buz p35/pcl p34 p33 p32 nc p50 p51 p52 p53 p54 v ss p55 p56 p57 p30 p31 p11/ani1 p10/ani0 av ss av ref av dd v dd x1 x2 ic reset nc 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34
8 m pd78081(a), 78082(a) ani0 to ani7 : analog input p100, p101 : port10 asck : asynchronous serial clock pcl : programmable clock av dd : analog power supply reset : reset av ref : analog reference voltage rxd : receive data av ss : analog ground sck2 : serial clock buz : buzzer clock si2 : serial input ic : internally connected so2 : serial output intp1 to intp3 : interrupt from peripherals ti5, ti6 : timer input nc : non-connection to5, to6 : timer output p00 to p03 : port0 txd : transmit data p10 to p17 : port1 v dd : power supply p30 to p37 : port3 v ss : ground p50 to p57 : port5 x1, x2 : crystal (main system clock) p70 to p72 : port7
9 m pd78081(a), 78082(a) 2. block diagram remark the internal rom and internal high-speed ram capacities depend on the product. p100/ti5/to5 p101/ti6/to6 si2/r x d/p70 so2/t x d/p71 sck2/asck/p72 ani0/p10 to ani7/p17 av dd av ss av ref intp1/p01 to intp3/p03 buz/p36 pcl/p35 port 0 port 1 port 3 port 5 port 7 port 10 system control 8-bit timer/ event counter 5 buzzer output interrupt control a/d converter serial interface 2 watchdog timer clock output control 8-bit timer/ event counter 6 78k/0 cpu core p00 p01 to p03 p10 to p17 p30 to p37 p50 to p57 p70 to p72 p100, p101 reset x1 x2 v dd v ss ic rom ram
10 m pd78081(a), 78082(a) 3. pin functions 3.1 port pins pin name input/output function after reset shared by: p00 input port 0 input only input ? p01 input/output 4-bit input/output port input/output is specifiable input intp1 p02 bit-wise. when used as the intp2 p03 input port, it is possible to intp3 connect a pull-up resistor by software. p10 to p17 input/output port 1 input ani0 to ani7 8-bit input/output port input/output is specifiable bit-wise. when used as the input port, it is possible to connect a pull-up resistor by software. note p30 to p34 input/output port 3 input ? p35 8-bit input/output port pcl p36 input/output is specifiable bit-wise. buz p37 when used as the input port, it is possible to connect ? a pull-up resistor by software. p50 to p57 input/output port 5 input ? 8-bit input/output port can drive up to seven leds directly. input/output is specifiable bit-wise. when used as the input port, it is possible to connect a pull-up resistor by software. p70 input/output port 7 input si2/rxd p71 3-bit input/output port so2/txd p72 input/output is specifiable bit-wise. sck2/asck when used as the input port, it is possible to connect a pull-up resistor by software. p100 input/output port 10 input ti5/to5 p101 2-bit input/output port ti6/to6 input/output is specifiable bit-wise. when used as the input port, it is possible to connect a pull-up resistor by software. note when p10/ani0 to p17/ani7 pins are used as the analog inputs for the a/d converter, set the port 1 to the input mode. the on-chip pull-up resistor is automatically disabled.
11 m pd78081(a), 78082(a) 3.2 non-port pins pin name input/output function after reset shared by: intp1 input external interrupt request input by which the active edge input p01 intp2 (rising edge, falling edge, or both rising and falling edges) can p02 intp3 be specified. p03 si2 input serial interface serial data input. input p70/rxd so2 output serial interface serial data output. input p71/txd sck2 input/output serial interface serial clock input/output. input p72/asck rxd input asynchronous serial interface serial data input. input p70/si2 txd output asynchronous serial interface serial data output. input p71/so2 asck input asynchronous serial interface serial clock input. input p72/sck2 ti5 input external count clock input to 8-bit timer (tm5). input p100/to5 ti6 external count clock input to 8-bit timer (tm6). p101/to6 to5 output 8-bit timer (tm5) output. input p100/ti5 to6 8-bit timer (tm6) output. p101/ti6 pcl output clock output. (for main system clock trimming) input p35 buz output buzzer output. input p36 ani0 to ani7 input a/d converter analog input. input p10 to p17 av ref input a/d converter reference voltage input. ? ? av dd ? a/d converter analog power supply. connected to v dd .?? av ss ? a/d converter ground potential. connected to v ss .?? reset input system reset input. ? ? x1 input main system clock oscillation crystal connection. ? ? x2 ? ?? v dd ? positive power supply. ? ? v ss ? ground potential. ? ? ic ? internal connection. connect directly to v ss .?? nc ? does not internally connected. connect to v ss .?? (it can be left open)
12 m pd78081(a), 78082(a) 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, refer to figure 3-1. table 3-1. input/output circuit type of each pin p00 2 input connect to v ss . p01/intp1 8-a input/output connect to v ss via a resistor individually. p02/intp2 p03/intp3 p10/ani0 to p17/ani7 11 input/output connect to v dd or v ss via a resistor individually. p30 to p32 5-a p33, p34 8-a p35/pcl 5-a p36/buz p37 p50 to p57 5-a p70/si2/rxd 8-a p71/so2/txd 5-a p72/sck2/asck 8-a p100/ti5/to5 8-a p101/ti6/to6 reset 2 input ? av ref ? ? connect to v ss . av dd connect to v dd . av ss connect to v ss . ic connect directly to v ss . nc connect to v ss (it can be left open). input/output circuit type pin name i/o recommended connection for unused pins
13 m pd78081(a), 78082(a) figure 3-1. pin input/output circuits type 2 in type 8-a pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd type 11 pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd type 5-a input enable schmitt-triggered input with hysteresis characteristic pullup enable data output disable input enable n-ch v dd p-ch in/out v dd p-ch p-ch n-ch v ref (threshold voltage) comparator +
14 m pd78081(a), 78082(a) 4. memory space the memory map of the m pd78081(a) and 78082(a) is shown in figure 4-1. figure 4-1. memory map note the internal rom and internal high-speed ram capacities depend on the product (see the following table). part number internal rom last address internal high-speed ram start address nnnnh mmmmh m pd78081(a) 1fffh fe00h m pd78082(a) 3fffh fd80h ffffh ff00h feffh mmmmh fee0h fedfh nnnnh + 1 nnnnh 0000h nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h use prohibited program area callf entry area program area callt table area vector table area special function registers (sfr) 256 8 bits general-purpose registers 32 8 bits internal high-speed ram note internal rom note program memory space data memory space mmmmh ?1
15 m pd78081(a), 78082(a) 5. peripheral hardware functions 5.1 ports input/output ports are classified into two types. cmos input (p00) : 1 cmos input/output (p01 to p03, port 1, port 3, port 5, port 7, port 10) : 32 total : 33 table 5-1. functions of ports port name pin name function port 0 p00 input only. p01 to p03 input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 1 p10 to p17 input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 3 p30 to p37 input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 5 p50 to p57 input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. led can be driven directly up to 7 pins. port 7 p70 to p72 input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 10 p100, p101 input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software.
16 m pd78081(a), 78082(a) 5.2 clock generator main system clock generator is incorporated. it is possible to change the minimum instruction execution time. 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (at main system clock frequency of 5.0 mhz) figure 5-1. clock generator block diagram 5.3 timer/event counter there are the following three timer/event counter channels: 8-bit timer/event counter : 2 channels watchdog timer : 1 channel table 5-2. types and functions of timer/event counters 8-bit timer/event counter 5, 6 watchdog timer type interval timer 2 channels 1 channel external event counter 2 channels ? function timer output 2 outputs ? pwm output 2 outputs ? square wave output 2 outputs ? interrupt request 2 1 x1 x2 stop clock to peripheral hardware cpu clock (f cpu ) 2 f xx 2 f xx 2 f xx 2 3 f x 2 main system clock oscillator division circuit prescaler standby control circuit prescaler selector selector 2 f xx 4 f x f xx
17 m pd78081(a), 78082(a) figure 5-2. 8-bit timer/event counter 5, 6 block diagram n = 5, 6 figure 5-3. watchdog timer block diagram f xx f xx 5 f xx 6 f xx 7 2 f xx 8 2 f xx 9 2 f xx 11 2 intwdt maskable interrupt request reset intwdt non-maskable interrupt request prescaler selector control circuit 4 22 2 8-bit counter f xx 3 2 internal bus 8-bit compare register (crn0) 8-bit timer register n (tmn) internal bus output control circuit selector 2f xx to f xx /2 9 f xx /2 11 ti5/p100/to5, ti6/p101/to6 clear ovf inttmn to5/p100/ti5, to6/p101/ti6 match
18 m pd78081(a), 78082(a) 5.4 clock output control circuit this circuit can output clocks of the following frequencies: 19.5 khz/39.1 khz/78.1 khz/156 khz/313 khz/625 khz/1.25 mhz/2.5 mhz/5.0 mhz (at main system clock frequency of 5.0 mhz) figure 5-4. clock output control circuit block diagram 5.5 buzzer output control circuit this circuit can output clocks of the following frequencies that can be used for driving buzzers: 1.2 khz/2.4 khz/4.9 khz/9.8 khz (at main system clock frequency of 5.0 mhz) figure 5-5. buzzer output control circuit block diagram pcl/p35 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 synchronization circuit f xx /2 f xx selector output control circuit selector output control circuit buz/p36 f xx /2 9 f xx /2 10 f xx /2 11
19 m pd78081(a), 78082(a) 5.6 a/d converter the a/d converter consists of eight 8-bit resolution channels. a/d conversion can be started by the following two methods: hardware starting software starting figure 5-6. a/d converter block diagram intp3/p03 tap selector ani0/p10 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 ani1/p11 av dd av ref av ss intad intp3 series resistor string selector sample & hold circuit voltage comparator successive approximation register (sar) edge detector control circuit a/d conversion result register (adcr) internal bus
20 m pd78081(a), 78082(a) 5.7 serial interface there is one on-chip serial interface channel synchronous with the clock. the serial interface channel 2 operates in the following two modes: 3-wire serial i/o mode : starting bit msb/lsb switching possible asynchronous serial interface (uart) mode : on-chip dedicated baud rate generator figure 5-7. serial interface channel 2 block diagram receive buffer register (rxb/sio2) internal bus direction control circuit direction control circuit transmit shift register (txs/sio2) receive shift register (rxs) receive control circuit transmit control circuit sck output control circuit baud rate generator intser intst intsr/intcsi2 f xx to f xx /2 10 asck/sck2/p72 t x d/so2/p71 r x d/si2/p70
21 m pd78081(a), 78082(a) 6. interrupt functions interrupt functions include three types and thirteen sources as shown below. non-maskable : 1 maskable : 11 software : 1 table 6-1. list of interrupt sources interrupt default internal/ vector basic table configuration type priority external address type non- ? intwdt overflow of watchdog timer (when the watchdog internal 0004h (a) maskable timer mode 1 is selected) maskable 0 intwdt overflow of watchdog timer (when the interval timer (b) mode is selected) 1 intp1 pin input edge detection external 0008h (c) 2 intp2 000ah 3 intp3 000ch 4 intser occurrence of serial interface channel 2 uart internal 0018h (b) reception error 5 intsr completion of serial interface channel 2 uart 001ah reception intcsi2 completion of serial interface channel 2 3-wire transfer 6 intst completion of serial interface channel 2 uart 001ch transmission 7 intad completion of a/d conversion 0028h 8 inttm5 generation of matching signal of 8-bit timer/event 002ah counter 5 9 inttm6 generation of matching signal of 8-bit timer/event 002ch counter 6 software ? brk execution of brk instruction ? 003eh (d) notes 1. default priority is the priority order when several maskable interrupt requests are generated at the same time. 0 is the highest order and 9 is the lowest order. 2. basic configuration types (a) to (d) correspond to (a) to (d) in figure 6-1. name trigger note 2 note 1 interrupt source
22 m pd78081(a), 78082(a) figure 6-1. interrupt function basic configuration (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt interrupt request standby release signal internal bus vector table address generator priority control circuit mk ie pr isp if interrupt request internal bus priority control circuit vector table address generator standby release signal if internal bus interrupt request edge detector vector table address generator standby release signal external interrupt mode register (intm0, intm1) mk ie pr isp priority control circuit
23 m pd78081(a), 78082(a) figure 6-1. interrupt function basic configuration (2/2) (d) software interrupt if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specification flag internal bus interrupt request vector table address generator priority control circuit
24 m pd78081(a), 78082(a) 7. standby function the standby function intends to reduce current consumption. it has the following two modes: halt mode : in this mode, the cpu operation clock is stopped. the average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. stop mode : in this mode, oscillation of the main system clock is stopped. all the operations performed on the main system clock are suspended, and power consumption becomes extremely small. figure 7-1. standby function 8. reset function there are the following two reset methods. external reset by reset pin internal reset by watchdog timer runaway time detection main system clock operation interrupt request stop instruction stop mode (oscillation of the main system clock is stopped.) interrupt request halt instruction halt mode (supply of clock to cpu is stopped although clock is generated.)
25 m pd78081(a), 78082(a) 9. instruction set (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz 2nd operand [hl + byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + b] $addr16 1 none 1st operand [hl + c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov note except r = a
26 m pd78081(a), 78082(a) (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand #word ax rp note sfrp saddrp !addr16 sp none 1st operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl 2nd operand [hl + byte] #byte a r sfr saddr !addr16 psw [de] [hl] [hl + b] $addr16 1 none 1st operand [hl + c] [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw
27 m pd78081(a), 78082(a) (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr 2nd operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none 1st operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz 2nd operand ax !addr16 !addr11 [addr5] $addr16 1st operand basic instruction br call callf callt br br bc bnc bz bnz compound instruction bt bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
28 m pd78081(a), 78082(a) parameter symbol test conditions ratings unit supply voltage v dd e0.3 to +7.0 v av dd e0.3 to v dd + 0.3 v av ref e0.3 to v dd + 0.3 v av ss e0.3 to +0.3 v input voltage v i e0.3 to v dd + 0.3 v output voltage v o e0.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pins av ss e 0.3 to av ref + 0.3 v output current, high i oh per pin e10 ma total of p10 to p17, p50 to p54, p70 to p72, e15 ma p100, p101 total of p01 to p03, p30 to p37, p55 to p57 e15 ma output current, low i ol note per pin peak value 30 ma r.m.s. value 15 ma total of p50 to p54 peak value 100 ma r.m.s. value 70 ma total of p55 to p57 peak value 100 ma r.m.s. value 70 ma total of p10 to p17, p70 to p72, peak value 50 ma p100, p101 r.m.s. value 20 ma total of p01 to p03, p30 to p37 peak value 50 ma r.m.s. value 20 ma operating ambient temperature t a e40 to +85 c storage temperature t stg e65 to +150 c 10. electrical specifications electrical specifications of m pd78081(a) and 78082(a) (1/11) absolute maximum ratings (t a = 25 c) note the r.m.s. value should be calculated as follows: [r.m.s. value] = [peak value] duty caution if the absolute maximum rating of even one of the above parameters is exceeded, the quality of the product may be degraded. the absolute maximum ratings are therefore the rated values that may, if exceeded, physically damage the product. be sure to use the product with all the absolute maximum ratings observed. capacitance (t a = 25 c, v dd = v ss = 0 v) remark unless otherwise specified, alternate-function pin characteristics are the same as port pin characteristics. parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz, unmeasured pins returned to 0 v. 15 pf i/o capacitance c io f = 1 mhz, p01 to p03, p10 to p17, p30 to 15 pf unmeasured pins p37, p50 to p57, p70 to p72, returned to 0 v. p100, p101
29 m pd78081(a), 78082(a) electrical specifications of m pd78081(a) and 78082(a) (2/11) main system clock oscillator characteristics (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. only the oscillator characteristics are shown. for the instruction execution time, refer to ac characteristics. 2. time required for oscillation to stabilize after a reset or the stop mode has been released. caution when using the oscillation circuit of the main system clock, wire the portion enclosed in broken lines in the figures as follows to avoid adverse influence on the wiring capacitance: keep the wiring length as short as possible. do not cross the wiring over other signal lines. do not route the wiring in the vicinity of lines through which a high fluctuating current flows. always keep the ground point of the capacitor of the oscillation circuit at the same potential as v ss . do not connect the ground pattern through which a high current flows. do not extract signals from the oscillation circuit. recommended circuit ceramic oscillation frequency v dd = oscillation voltage 1.0 5.0 mhz resonator (f x ) note 1 range oscillation stabilization after v dd came to min. 4 ms time note 2 of oscillation voltage range crystal oscillation frequency 1.0 5.0 mhz resonator (f x ) note 1 oscillation stabilization v dd = 4.5 to 5.5 v 10 ms time note 2 30 external clock x1 input frequency 1.0 5.0 mhz (f x ) note 1 x1 input high-/low-level 85 500 ns widths (t xh , t xl ) resonator parameter test conditions min. typ. max. unit ic c1 x1 c2 x2 ic c1 x1 c2 x2 x2 x1 pd74hcu04 m
30 m pd78081(a), 78082(a) parameter symbol test conditions min. typ. max. unit input voltage, high v ih1 p10 to p17, p30 to v dd = 2.7 to 5.5 v 0.7 v dd v dd v p32, p35 to p37, p50 to p57, p71 v ih2 p00 to p03, p33, p34, v dd = 2.7 to 5.5 v 0.8 v dd v dd v p70, p72, p100, p101, reset v ih3 x1, x2 v dd = 2.7 to 5.5 v v dd e 0.5 v dd v v dd e 0.2 v dd v input voltage, low v il1 p10 to p17, p30 to v dd = 2.7 to 5.5 v 0 0.3 v dd v p32, p35 to p37, p50 to p57, p71 v il2 p00 to p03, p33, p34, v dd = 2.7 to 5.5 v 0 0.2 v dd v p70, p72, p100, p101, reset v il3 x1, x2 v dd = 2.7 to 5.5 v 0 0.4 v 0 0.2 v output voltage, high v oh v dd = 4.5 to 5.5 v, i oh = e1 ma v dd e 1.0 v i oh = e100 m av dd e 0.5 v output voltage, low v ol p50 to p57 v dd = 2.0 to 4.5 v, 0.8 v i ol = 10 ma v dd = 4.5 to 5.5 v, 0.4 2.0 v i ol = 15 ma p01 to p03, p10 to v dd = 4.5 to 5.5 v, 0.4 v p17, p30 to p37, p70 i ol = 1.6 ma to p72, p100, p101 i ol = 400 m a 0.5 v input leak current, high i lih1 v in = v dd p00 to p03, p10 to p17, 3 m a p30 to p37, p50 to p57, p70 to p72, p100, p101, reset i lih2 x1, x2 20 m a input leak current, low i lil1 v in = 0 v p00 to p03, p10 to p17, e3 m a p30 to p37, p50 to p57, p70 to p72, p100, p101, reset i lil2 x1, x2 e20 m a output leak current, high i loh v out = v dd 3 m a output leak current, low i lol v out = 0 v e3 m a software pull-up resistance r v in = 0 v p01 to p03, p10 to p17, 15 40 90 k w p30 to p37, p50 to p57, p70 to p72, p100, p101 remark unless otherwise specified, alternate-function pin characteristics are the same as port pin characteristics. 0.8 v dd 0.85 v dd 0 0 0.15 v dd v dd v v dd v v v electrical specifications of m pd78081(a) and 78082(a) (3/11) dc characteristics (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) 0.2 v dd
31 m pd78081(a), 78082(a) electrical specifications of m pd78081(a) and 78082(a) (4/11) dc characteristics (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit supply current note 1 i dd1 5.0-mhz crystal oscil- v dd = 5.0 v 10% note 4 4.5 13.5 ma lation operating mode v dd = 3.0 v 10% note 5 0.7 2.1 ma (f xx = 2.5 mhz) note 2 v dd = 2.0 v 10% note 5 0.4 1.2 ma 5.0-mhz crystal oscil- v dd = 5.0 v 10% note 4 8.0 24.0 ma lation operating mode v dd = 3.0 v 10% note 5 0.9 2.7 ma (f xx = 5.0 mhz) note 3 i dd2 5.0-mhz crystal oscil- v dd = 5.0 v 10% 1.4 4.2 ma lation halt mode v dd = 3.0 v 10% 0.5 1.5 ma (f xx = 2.5 mhz) note 2 v dd = 2.0 v 10% 280 840 m a 5.0-mhz crystal oscil- v dd = 5.0 v 10% 1.6 4.8 ma lation halt mode v dd = 3.0 v 10% 0.65 1.95 ma (f xx = 5.0 mhz) note 3 i dd3 stop mode v dd = 5.0 v 10% 0.1 30 m a v dd = 3.0 v 10% 0.05 10 m a v dd = 2.0 v 10% 0.05 10 m a notes 1. not including av ref and av dd currents or port currents (including current flowing into on-chip pull-up resistors). 2. f xx = f x /2 operation (when oscillation mode selection register (osms) is set to 00h). 3. f xx = f x operation (when oscillation mode selection register (osms) is set to 01h). 4. high-speed mode operation (when processor clock control register (pcc) is set to 00h). 5. low-speed mode operation (when processor clock control register (pcc) is set to 04h). remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency
32 m pd78081(a), 78082(a) parameter symbol test conditions min. typ. max. unit cycle time t cy f xx = f x /2 note 1 v dd = 2.7 to 5.5 v 0.8 64 m s (minimum instruction execution 2.0 64 m s time) f xx = f x note 2 3.5 v v dd 5.5 v 0.4 32 m s 2.7 v v dd < 3.5 v 0.8 32 m s ti5, ti6 f ti v dd = 4.5 to 5.5 v 0 4 mhz input frequency 0 275 khz ti5, ti6 input high-/ t tih ,v dd = 4.5 to 5.5 v 100 ns low-level widths t til 1.8 m s interrupt request input high-/ t inth ,v dd = 2.7 to 5.5 v 10 m s low-level widths t intl 20 m s reset low-level width t rsl v dd = 2.7 to 5.5 v 10 m s 20 m s electrical specifications of m pd78081(a) and 78082(a) (5/11) ac characteristics (1) basic operation (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. when oscillation mode selection register (osms) is set to 00h. 2. when osms is set to 01h. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency t cy vs v dd t cy vs v dd (main system clock f xx = f x /2 operation) (main system clock f xx = f x operation) 60 10 2.0 1.0 0.5 0.4 0 123456 power suppl y volta g e v dd [v] cycle time t cy [ s] m operation guaranteed range 60 10 2.0 1.0 0.5 0.4 0 123456 power suppl y volta g e v dd [v] cycle time t cy [ s] m operation guaranteed range
33 m pd78081(a), 78082(a) parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy2 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 4,800 ns sck2 high-/low-level t kh2 , t kl2 4.5 v v dd 5.5 v 400 ns widths 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1,600 ns 2,400 ns si2 setup time t sik2 v dd = 2.0 to 5.5 v 100 ns (to sck2 - ) 150 ns si2 hold time t ksi2 400 ns (from sck2 - ) so2 output delay time t kso2 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns from sck2 500 ns sck2 rise/fall time t r2 , t f2 1,000 ns parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy1 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 4,800 ns sck2 high-/low-level t kh1 , t kl1 v dd = 4.5 to 5.5 v t kcy1 /2 e 50 ns widths t kcy1 /2 e 100 ns si2 setup time t sik1 4.5 v v dd 5.5 v 100 ns (to sck2 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si2 hold time t ksi1 400 ns (from sck2 - ) so2 output delay time t kso1 c = 100 pf note 300 ns from sck2 electrical specifications of m pd78081(a) and 78082(a) (6/11) (2) serial interface (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (sck2... internal clock output) note c is the load capacitance of sck2 and so2 output lines. (b) 3-wire serial i/o mode (sck2... external clock input) note c is the load capacitance of so2 output line.
34 m pd78081(a), 78082(a) parameter symbol conditions min. typ. max. unit asck cycle time t kcy3 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 4,800 ns asck high-/low-level t kh3 , t kl3 4.5 v v dd 5.5 v 400 ns widths 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1,600 ns 2,400 ns transfer rate 4.5 v v dd 5.5 v 39,063 bps 2.7 v v dd < 4.5 v 19,531 bps 2.0 v v dd < 2.7 v 9,766 bps 6,510 bps asck rise/fall time t r3 , t f3 1,000 ns electrical specifications of m pd78081(a) and 78082(a) (7/11) (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.5 v v dd 5.5 v 78,125 bps 2.7 v v dd < 4.5 v 39,063 bps 2.0 v v dd < 2.7 v 19,531 bps 9,766 bps (d) uart mode (external clock input)
35 m pd78081(a), 78082(a) electrical specifications of m pd78081(a) and 78082(a) (8/11) ac timing test points (excluding x1 input) ti timing clock timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points t xl t xh 1/f x v ih3 (min.) v il3 (max.) x1 input ti5, ti6 1/f ti t tih t til
36 m pd78081(a), 78082(a) electrical specifications of m pd78081(a) and 78082(a) (9/11) serial transfer timing 3-wire serial i/o mode : parameter symbol conditions min. typ. max. unit 8 8 8 bit 2.7 v av ref av dd 0.6 % 1.8 v av ref < 2.7 v 1.4 % t conv 2.0 v av dd 5.5 v 19.1 200 m s 1.8 v av dd < 2.0 v 38.2 200 m s t samp 12/fxx m s v ian av ss av ref v av ref 1.8 av dd v r airef 4 14 k w a/d converter characteristics (t a = e40 to +85 c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) uart mode (external clock input) : resolution overall error note conversion time sampling time analog input voltage reference voltage resistance between av ref and av ss note overall error excluding quantization error ( 1/2lsb). it is indicated as a ratio to the full-scale value. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency t kcy1, 2 t kl1, 2 t kh1, 2 sck2 si2 so2 t sik1, 2 t ksi1, 2 t kso1, 2 input data output data t r2 t f2 t kcy3 t kh3 t kl3 t f3 t r3 asck
37 m pd78081(a), 78082(a) parameter symbol conditions min. typ. max. unit data retention power v dddr 1.8 5.5 v supply voltage data retention power i dddr v dddr = 1.8 v 0.1 10 m a supply current release signal set time t srel 0 m s oscillation stabilization t wait release by reset 2 17 /fx ms wait time release by interrupt request note ms electrical specifications of m pd78081(a) and 78082(a) (10/11) data memory stop mode low supply voltage data retention characteristics (t a = e40 to +85 c) data retention timing (standby release signal: stop mode release by interrupt request signal) note in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register (osts), selection of 2 12 /f xx and 2 14 /f xx to 2 17 /f xx is possible. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode release by reset) t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr
38 m pd78081(a), 78082(a) electrical specifications of m pd78081(a) and 78082(a) (11/11) interrupt request input timing reset input timing t intl t inth intp1 to intp3 t rsl reset
39 m pd78081(a), 78082(a) parameter symbol test conditions ratings unit supply voltage v dd e0.3 to +7.0 v av dd e0.3 to v dd + 0.3 v av ref e0.3 to v dd + 0.3 v av ss e0.3 to +0.3 v input voltage v i e0.3 to v dd + 0.3 v output voltage v o e0.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pins av ss e 0.3 to av ref + 0.3 v output current, high i oh per pin e10 ma total of p10 to p17, p50 to p54, p70 to p72, e15 ma p100, p101 total of p01 to p03, p30 to p37, p55 to p57 e15 ma output current, low i ol note per pin peak value 30 ma r.m.s. value 15 ma total of p50 to p54 peak value 100 ma r.m.s. value 70 ma total of p55 to p57 peak value 100 ma r.m.s. value 70 ma total of p10 to p17, p70 to p72, peak value 50 ma p100, p101 r.m.s. value 20 ma total of p01 to p03, p30 to p37 peak value 50 ma r.m.s. value 20 ma operating ambient temperature t a e40 to +125 c storage temperature t stg e65 to +150 c electrical specifications of m pd78081(a2) (1/10) absolute maximum ratings (t a = 25 c) note the r.m.s. value should be calculated as follows: [r.m.s. value] = [peak value] duty caution if the absolute maximum rating of even one of the above parameters is exceeded, the quality of the product may be degraded. the absolute maximum ratings are therefore the rated values that may, if exceeded, physically damage the product. be sure to use the product with all the absolute maximum ratings observed. permissible pin sink current characteristics with overvoltage applied pending capacitance (t a = 25 c, v dd = v ss = 0 v) remark unless otherwise specified, alternate-function pin characteristics are the same as port pin characteristics. parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz, unmeasured pins returned to 0 v. 15 pf i/o capacitance c io f = 1 mhz, p01 to p03, p10 to p17, p30 to 15 pf unmeasured pins p37, p50 to p57, p70 to p72, returned to 0 v. p100, p101
40 m pd78081(a), 78082(a) electrical specifications of m pd78081(a2) (2/10) main system clock oscillator characteristics (t a = e40 to +125 c, v dd = 5 v 10%) notes 1. only the oscillator characteristics are shown. for the instruction execution time, refer to ac characteristics. 2. time required for oscillation to stabilize after a reset or the stop mode has been released. caution when using the oscillation circuit of the main system clock, wire the portion enclosed in broken lines in the figure as follows to avoid adverse influence on the wiring capacitance: keep the wiring length as short as possible. do not cross the wiring over other signal lines. do not route the wiring in the vicinity of lines through which a high fluctuating current flows. always keep the ground point of the capacitor of the oscillation circuit at the same potential as v ss . do not connect the ground pattern through which a high current flows. do not extract signals from the oscillation circuit. recommended circuit crystal oscillation frequency 1.0 7.0 mhz resonator (f x ) note 1 oscillation stabilization 10 ms time note 2 external clock x1 input frequency 1.0 7.0 mhz (f x ) note 1 x1 input high-/low-level 64 500 ns widths (t xh , t xl ) resonator parameter test conditions min. typ. max. unit ic c1 x1 c2 x2 x2 x1 pd74hcu04 m
41 m pd78081(a), 78082(a) parameter symbol test conditions min. typ. max. unit input voltage, high v ih1 p10 to p17, p30 to p32, p35 to p37, p50 to 0.7 v dd v dd v p57 v ih2 p00 to p03, p33, p34, p70 to p72, p100, 0.9 v dd v dd v p101, reset v ih3 x1, x2 v dd e 0.2 v dd v input voltage, low v il1 p10 to p17, p30 to p32, p35 to p37, p50 to 0 0.3 v dd v p57 v il2 p00 to p03, p33, p34, p70 to p72, p100, 0 0.16 v dd v p101, reset v il3 x1, x2 0 0.4 v output voltage, high v oh i oh = e1 ma v dd e 1.0 v i oh = e100 m av dd e 0.5 v output voltage, low v ol p50 to p57 i ol = 15 ma 0.4 2.2 v p01 to p03, p10 to i ol = 1.6 ma 0.45 v p17, p30 to p37, p70 i ol = 400 m a 0.5 v to p72, p100, p101 input leak current, high i lih1 v in = v dd p00 to p03, p10 to p17, 10 v p30 to p37, p50 to p57, p70 to p72, p100, p101, reset i lih2 x1, x2 20 m a input leak current, low i lil1 v in = 0 v p00 to p03, p10 to p17, e10 m a p30 to p37, p50 to p57, p70 to p72, p100, p101, reset i lil2 x1, x2 e20 m a output leak current, high i loh v out = v dd 10 m a output leak current, low i lol v out = 0 v e10 m a software pull-up resistance r v in = 0 v p01 to p03, p10 to p17, 15 40 120 k w p30 to p37, p50 to p57, p70 to p72, p100, p101 supply current note 1 i dd1 7.0-mhz crystal oscillation operating mode 9.0 29.0 ma (f xx = 3.5 mhz) notes 2, 3 5.0-mhz crystal oscillation operating mode 5.5 16.5 ma (f xx = 2.5 mhz) notes 2, 3 i dd2 7.0-mhz crystal oscillation halt mode 1.5 7.2 ma (f xx = 3.5 mhz) note 2 5.0-mhz crystal oscillation halt mode 1.2 6.5 ma (f xx = 2.5 mhz) note 2 i dd3 stop mode 0.1 1,000 m a notes 1. not including av ref and av dd currents or port currents (including current flowing into on-chip pull-up resistors). 2. f xx = f x /2 operation (when oscillation mode selection register (osms) is set to 00h). 3. high-speed mode operation (when processor clock control register (pcc) is set to 00h). remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. unless otherwise specified, alternate-function pin characteristics are the same as port pin characteristics. electrical specifications of m pd78081(a2) (3/10) dc characteristics (t a = e40 to +125 c, v dd = 5 v 10%)
42 m pd78081(a), 78082(a) parameter symbol test conditions min. typ. max. unit cycle time (minimum t cy f xx = f x /2 note 0.57 32 m s instruction execution time) ti5, ti6 input frequency f ti 0 2 khz ti5, ti6 input high-/ t tih , t til 200 ns low-level widths interrupt request input high-/ t inth , t intl 10 m s low-level widths reset low-level width t rsl 10 m s electrical specifications of m pd78081(a2) (4/10) ac characteristics (1) basic operation (t a = e40 to +125 c, v dd = 5 v 10%) note when oscillation mode selection register (osms) is set to 00h. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency t cy vs v dd (main system clock f xx = f x /2 operation) 60 10 2.0 1.0 0.5 0 123456 power suppl y volta g e v dd [ v ] operation guaranteed range cycle time t cy [ s] m
43 m pd78081(a), 78082(a) parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy2 1,000 ns sck2 high-/low-level t kh2 , t kl2 500 ns widths si2 setup time t sik2 150 ns (to sck2 - ) si2 hold time t ksi2 500 ns (from sck2 - ) so2 output delay time t kso2 c = 100 pf note 400 ns from sck2 sck2 rise/fall time t r2 , t f2 1,000 ns parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy1 1,000 ns sck2 high-/low-level t kh1 , t kl1 t kcy1 /2 e 100 ns widths si2 setup time t sik1 150 ns (to sck2 - ) si2 hold time t ksi1 500 ns (from sck2 - ) so2 output delay time t kso1 c = 100 pf note 400 ns from sck2 electrical specifications of m pd78081(a2) (5/10) (2) serial interface (t a = e40 to +125 c, v dd = 5 v 10%) (a) 3-wire serial i/o mode (sck2... internal clock output) note c is the load capacitance of sck2 and so2 output lines. (b) 3-wire serial i/o mode (sck2... external clock input) note c is the load capacitance of so2 output line.
44 m pd78081(a), 78082(a) parameter symbol conditions min. typ. max. unit asck cycle time t kcy3 1,000 ns asck high-/low-level t kh3 , t kl3 500 ns widths transfer rate 38,462 bps asck rise/fall time t r3 , t f3 1,000 ns electrical specifications of m pd78081(a2) (6/10) (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 76,923 bps (d) uart mode (external clock input)
45 m pd78081(a), 78082(a) electrical specifications of m pd78081(a2) (7/10) ac timing test points (excluding x1 input) ti timing clock timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points t xl t xh 1/f x v dd ?0.2 v 0.4 v x1 input ti5, ti6 1/f ti t tih t til
46 m pd78081(a), 78082(a) electrical specifications of m pd78081(a2) (8/10) serial transfer timing 3-wire serial i/o mode : parameter symbol conditions min. typ. max. unit 8 8 8 bit 4.5 v av ref av dd 1.0 % t conv 23.8 100 m s t samp 12/fxx m s v ian av ss av ref v av ref 4.5 av dd v r airef 4 14 k w a/d converter characteristics (t a = e40 to +125 c, av dd = v dd = 5 v 10%, av ss = v ss = 0 v) uart mode (external clock input) : resolution overall error note conversion time sampling time analog input voltage reference voltage resistance between av ref and av ss note overall error excluding quantization error ( 1/2lsb). it is indicated as a ratio to the full-scale value. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency t kcy1, 2 t kl1, 2 t kh1, 2 sck2 si2 so2 t sik1, 2 t ksi1, 2 t kso1, 2 input data output data t r2 t f2 t kcy3 t kh3 t kl3 t f3 t r3 asck
47 m pd78081(a), 78082(a) parameter symbol conditions min. typ. max. unit data retention power v dddr 4.5 5.5 v supply voltage data retention power i dddr v dddr = 4.5 v 0.1 1,000 m a supply current release signal set time t srel 0 m s oscillation stabilization t wait release by reset 2 17 /fx ms wait time release by interrupt request note ms electrical specifications of m pd78081(a2) (9/10) data memory stop mode low supply voltage data retention characteristics (t a = e40 to +125 c) data retention timing (standby release signal: stop mode release by interrupt request signal) note in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register (osts), selection of 2 12 /f xx and 2 14 /f xx to 2 17 /f xx is possible. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode release by reset) t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr
48 m pd78081(a), 78082(a) electrical specifications of m pd78081(a2) (10/10) interrupt request input timing reset input timing t intl t inth intp1 to intp3 t rsl reset
49 m pd78081(a), 78082(a) 11. package drawings m pd78081gb(a)- -3b4, 78082gb(a)- -3b4, 78081gb(a2)- -3b4 remark the shape and material of es versions are the same as those of mass-produced versions. 44 pin plastic qfp ( 10) note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. p44gb-80-3b4-3 item millimeters inches a b c 13.6 0.4 10.0 0.2 10.0 0.2 0.535 0.394 0.394 d 13.6 0.4 0.535 f 1.0 0.039 g 1.0 0.039 h 0.35 0.10 0.014 i 0.15 0.006 j 0.8 (t.p.) 0.031 (t.p) k 1.8 0.2 0.071 l 0.8 0.2 0.031 m 0.15 0.006 n 0.10 0.004 p 2.7 0.106 q 0.1 0.1 0.004 0.004 r5 5 5 5 s 3.0 max. 0.119 max. +0.017 ?.016 +0.008 ?.009 +0.008 ?.009 +0.017 ?.016 +0.004 ?.005 +0.008 ?.009 +0.009 ?.008 +0.004 ?.003 n l detail of lead end g m i j h a f m q r b 33 34 22 44 1 12 11 23 c d s p k +0.10 ?.05
50 m pd78081(a), 78082(a) m pd78081gb(a)- -3bs-mtx, 78082gb(a)- -3bs-mtx 44 pin plastic qfp ( 10) s44gb-80-3bs item millimeters inches n p q 0.125 0.075 0.10 2.7 0.004 0.106 0.005 0.003 note each lead centerline is located within 0.16 mm (0.007 inch) of its true position (t.p.) at maximum material condition. j i h n a 13.2 0.2 0.520 +0.008 ?.009 b 10.0 0.2 0.394 +0.008 ?.009 c 10.0 0.2 0.394 +0.008 ?.009 d 13.2 0.2 0.520 +0.008 ?.009 f g h 1.0 0.37 1.0 0.039 0.039 0.015 +0.003 ?.004 i j k 0.8 (t.p.) 1.6 0.2 0.16 0.007 0.031 (t.p.) 0.063 0.008 l 0.8 0.2 0.031 +0.009 ?.008 m 0.17 0.007 +0.002 ?.003 s 3.0 max. 0.119 max. r3 3 +7 ? +0.08 ?.07 +0.06 ?.05 +7 ? detail of lead end q f g k m l r m 33 34 22 44 1 12 11 23 s p cd a b
51 m pd78081(a), 78082(a) 12. recommended soldering conditions m pd78081(a) and 78082(a) should be soldered and mounted under the conditions recommended in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, consult our sales representative. table 12-1. surface mounting type soldering conditions m pd78081gb(a)- -3b4 : 44-pin plastic qfp (10 10 mm) m pd78082gb(a)- -3b4 : 44-pin plastic qfp (10 10 mm) m pd78081gb(a2)- -3b4 : 44-pin plastic qfp (10 10 mm) package peak temperature: 235 c, reflow time: 30 seconds or below (at 210 c or higher), number of reflow processes: 3 max. package peak temperature: 215 c, reflow time: 40 seconds or below (at 200 c or higher), number of reflow processes: 3 max. solder temperature: 260 c or below, flow time: 10 seconds or below, number of flow processes: once, preheating temperature: 120 c or below (package surface tem- perature) pin temperature: 300 c or below, time: 3 seconds or below (per device side) soldering conditions symbol ir35-00-3 soldering method wave soldering vps infrared reflow ? ws60-00-1 vp15-00-3 pin partial heating cautions 1. use of more than one soldering method should be avoided (except for the pin partial heating method). 2. because production of the m pd78081gb(a)- -3bs-mtx and 78082gb(a)- -3bs-mtx is still in a planning stage, their soldering conditions are pending.
52 m pd78081(a), 78082(a) appendix a. development tools the following development tools are available to support development of systems using the m pd78081(a) and 78082(a). language processing software ra78k/0 notes 1, 2, 3, 4 assembler package common to the 78k/0 series cc78k/0 notes 1, 2, 3, 4 c compiler package common to the 78k/0 series df78083 notes 1, 2, 3, 4 device file used for the m pd78083 subseries cc78k/0-l notes 1, 2, 3, 4 c compiler library source file common to the 78k/0 series prom writing tools pg-1500 prom programmer pa-78p083gb programmer adapter connected to the pg-1500 pg-1500 controller notes 1, 2 control program for the pg-1500 debugging tools ie-78000-r in-circuit emulator common to the 78k/0 series ie-78000-r-a in-circuit emulator common to the 78k/0 series (for integrated debugger) ie-78000-r-bk break board common to the 78k/0 series ie-78078-r-em emulation board common to the m pd78078 subseries ep-78083gb-r emulation probe for the m pd78083 subseries ev-9200g-44 socket mounted on the target system board prepared for 44-pin plastic qfp sm78k0 notes 5, 6, 7 system simulator common to the 78k/0 series id78k0 notes 4, 5, 6, 7 integrated debugger for the ie-78000-r-a sd78k/0 notes 1, 2 screen debugger for the ie-78000-r df78083 notes 1, 2, 5, 6, 7 device file used for the m pd78083 subseries notes 1. based on pc-9800 series (ms-dos tm ) 2. based on ibm pc/at tm and its compatibles (pc dos tm /ibm dos tm /ms-dos) 3. based on hp9000 series 300 tm (hp-ux tm ) 4. based on hp9000 series 700 tm (hp-ux), sparcstation tm (sunos tm ), and ews4800 series (ews-ux/ v) 5. based on pc-9800 series (ms-dos + windows tm ) 6. based on ibm pc/at and its compatibles (pc dos/ibm dos/ms-dos + windows) 7. based on news tm (news-os tm ) remarks 1. please refer to the 78k/0 series selection guide (u11126e) for information on the third party development tools. 2. use the ra78k/0, cc78k/0, sm78k0, id78k0, and sd78k/0 in combination with the df78083.
53 m pd78081(a), 78082(a) real-time os mx78k0 notes 1, 2, 3, 4 os used for the 78k/0 series fuzzy inference development support system fe9000 note 1 /fe9200 note 5 fuzzy knowledge data input tool ft9080 note 1 /ft9085 note 2 translator fi78k0 notes 1, 2 fuzzy inference module fd78k0 notes 1, 2 fuzzy inference debugger notes 1. based on pc-9800 series (ms-dos) 2. based on ibm pc/at and its compatibles (pc dos/ibm dos/ms-dos) 3. based on hp9000 series 300 (hp-ux) 4. based on hp9000 series 700 (hp-ux), sparcstation (sunos), and ews4800 series (ews-ux/v) 5. based on ibm pc/at (pc dos/ibm dos/ms-dos + windows) remark please refer to the 78k/0 series selection guide (u11126e) for information on the third party development tools.
54 m pd78081(a), 78082(a) appendix b. related documents documents related to devices document name document no. japanese english m pd78083 subseries user?s manual u12176j ieu-1407 m pd78081(a), 78082(a) data sheet u12436j this document m pd78p083(a) data sheet u12175j u12175e 78k/0 series user?s manual instructions u12326j ieu-1372 78k/0 series instruction table u10903j ? 78k/0 series instruction set u10904j ? m pd78083 subseries special function register table iem-5599 ? 78k/0 series application note fundamental (iii) iea-767 u10182e documents related to development tools (user?s manual) (1/2) document name document no. japanese english ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 ra78k0 assembler package operation u11802j u11802e assembly language u11801j u11801e structured assembly u11789j u11789e language cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k0 c compiler operation u11517j u11517e language u11518j u11518e cc78k/0 c compiler application note programming eea-618 eea-1208 know-how cc78k series library source file u12322j ? pg-1500 prom programmer u11940j eeu-1335 pg-1500 controller pc-9800 series (ms-dos) based eeu-704 eeu-1291 pg-1500 controller ibm pc series (pc dos) based eeu-5008 u10540e ie-78000-r u11376j u11376e ie-78000-r-a u10057j u10057e ie-78000-r-bk eeu-867 eeu-1427 ie-78078-r-em u10775j u10775e ep-78083 eeu-5003 eeu-1529 sm78k0 system simulator windows based reference u10181j u10181e sm78k series system simulator external part user open u10092j u10092e interface specifications id78k0 integrated debugger ews based reference u11151j ? id78k0 integrated debugger pc based reference u11539j u11539e id78k0 integrated debugger windows based guide u11649j u11649e caution the contents of the documents listed above are subject to change without prior notice. make sure to use the latest edition when starting design.
55 m pd78081(a), 78082(a) documents related to development tools (user?s manual) (2/2) document name document no. japanese english sd78k/0 screen debugger introduction eeu-852 u10539e pc-9800 series (ms-dos) based reference u10952j ? sd78k/0 screen debugger introduction eeu-5024 eeu-1414 ibm pc/at (pc dos) based reference u11279j u11279e documents related to embedded software (user?s manual) document name document no. japanese english 78k/0 series os mx78k0 basic u12257j ? fuzzy knowledge data input tools eeu-829 eeu-1438 78k/0, 78k/ii, and 87ad series fuzzy inference development support system eeu-862 eeu-1444 translator 78k/0 series fuzzy inference development support system eeu-858 eeu-1441 fuzzy inference module 78k/0 series fuzzy inference development support system eeu-921 eeu-1458 fuzzy inference debugger other documents document name document no. japanese english ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e electrostatic discharge (esd) test mem-539 ? guide to quality assurance for semiconductor devices c11893j mei-1202 microcomputer product series guide u11416j ? caution the contents of the documents listed above are subject to change without prior notice. make sure to use the latest edition when starting design.
56 m pd78081(a), 78082(a) [memo]
57 m pd78081(a), 78082(a) [memo]
58 m pd78081(a), 78082(a) notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
59 m pd78081(a), 78082(a) nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
m pd78081(a), 78082(a) 60 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 fip and iebus are trademarks of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such.

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